1. Field of the Invention
This invention relates to a microprocessor controlled communications controller and more particularly to the stretching of the microprocessor clock cycle signals.
2. Description of the Prior Art
Communications controllers are used in the communications field to accommodate the transfer of information between a communication transmission line and a data processing system.
The communications controller includes a microprocessor for controlling the communications controller, a random access memory for storing microprocessor program instructions, universal synchronous receiver transmitters (USRTs) for controlling the flow of data between the communication lines, and the communications controller. U.S. Pat. No. 4,291,371 which issued Sept. 22, 1981 entitled, "I/O Request Interrupt Mechanism" describes such a communications controller.
However, additional requirements were placed on such systems. Additional communication lines were coupled to such a system. Different kinds of communication devices were added such as Automatic Dialing units, Touch Tone Receivers, higher performance MODEMs, CRT terminals, etc. As a result, higher speed microprocessors and random access memories replaced their slower speed counterparts. The logic of the controller was also rearranged to provide common logic on a printed circuit board and individual logic associated with each device on separate smaller printed circuit boards.
This presented the problem of determining the speed at which the microprocessor would operate. The microprocessor could operate with memory at high speed but was limited to a slower speed when operating with the USRTs or the smaller printed circuit board. The operating speed of the prior art systems was limited to the speed of the slowest logic unit that was operative with the microprocessor. A solution was to have the microprocessor operate at high speed with faster logic units and at lower speed with the slower logic units.
U.S. Pat. No. 4,050,096 entitled, "Pulse Expanding System for Microprocessor Systems with Slow Memory" describes a clocking system whereby the length of a clocking pulse expanded to be operative with memory locations having longer access time. This approach, however, does provide the two clock rates needed to be operative with fast and slow logic speeds.
U.S. Pat. No. 4,040,021 entitled, "Circuit for Increasing the Apparent Occupancy of a Processor" describes a system which includes provisions for executing flagged instructions with standard machine timing and for executing unflagged instructions with extended machine timing. This requires two clock signal lines with the ability to suppress periodic timing pulses on one of the signal lines.
A number of other U.S. patents describe the modification of clocking pulses; however, they all have the disadvantage of using delay lines with their inherent higher cost. These include: U.S. Pat. No. 4,105,978 entitled, "Stretch and Stall Clock"; U.S. Pat. No. 3,594,733 entitled, "Digital Pulse Stretcher"; U.S. Pat. No. 3,543,295 entitled, "Circuits for Changing Pulse Train Repetition Rates"; U.S. Pat. No. 3,418,498 entitled, "Delay Line Timing Circuit for Use with Computer or Other Timed Operation Devices"; U.S. Pat. No. 3,593,158 entitled, "Variable Frequency Pulse Generator"; U.S. Pat. No. 3,775,696 entitled, "Synchronous Digital System Having A Multispeed Logic Clock Oscillator"; and U.S. Pat. No. 4,134,073 entitled, "Clock System Having Adaptive Synchronization Feature".